# Synchronous Sequential Logic Part I

Synchronous Sequential Logic Part I Mantksal Tasarm BBM231 M. nder Efe [email protected] 1 Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs are entirely defined by the current inputs However, many digital systems encountered everyday life are sequential (i.e. they have memory) the memory elements remember past inputs outputs of sequential circuits are not only dependent on the current input but also the state of the memory elements. 2 Sequential Circuits Model inputs outputs Combinational Circuit current state next state Memory Elements current state is a function of past inputs and initial state 3 Classification 1/2 Two types of sequential circuits 1. Synchronous Signals affect the memory elements at discrete instants of time. Discrete instants of time requires synchronization. Synchronization is usually achieved through the use of a common clock. A clock generator is a device that generates a periodic train of pulses. 4 Classification 2/2 1. Synchronous The state of the memory elements are updated with the arrival of each pulse This type of logical circuit is also known as clocked sequential circuits. 2. Asynchronous No clock behavior of an asynchronous sequential circuits depends upon the input signals at any instant of time and the order in which the inputs change.

Memory elements in asynchronous circuits are regarded as timedelay elements 5 Clocked Sequential Circuits Memory elements are flip-flops which are logic devices, each of which is capable of storing one bit of information. inputs outputs Combinational Circuit current state next state Flip-Flops clock 6 Clocked Sequential Circuits The outputs of a clocked sequential circuit can come from the combinational circuit, from the outputs of the flip-flops or both. The state of the flip-flops can change only during a clock pulse transition i.e. low-to-high and high-to-low clock edge When the clock maintains its value, the flip-flop output does not change The transition from one state to the next occurs at the clock edge. 7 Machine Machine( Inputs {X}, States {D}, Outputs {Z}, Output Function {F : XDZ}, Next State Function {G : XDD}) 8 Representation with State Diagram x1 x2 xi d1 d2 di dj ,z dr-1

dr 9 xl Assign a Node to Each State xp/zp xk/zk di dj Machine is at state di, input xk comes, the next state will be di and the output is zk Machine is at state di, input xp comes, the next state will be dj and the output is zp 10 Notation Let Ik be an input sequence with length equals to k, i.e. Ik = x1x2xk f(Ik,di) = z1z2zk is an output sequence g(Ik,di) = di1di2dik is a state sequence di Ik dik Follower of di after the input sequence Ik 11 Example - Fill out the rest 0 1 A E, 0 D, 1 B F, 0 C E, 0 B, 1 D F, 0 B, 0 E C, 0 F, 1 F B, 0 C, 0 A

E D C B F D, 0 12 Example 0 1 A E, 0 D, 1 B F, 0 C E, 0 B, 1 D F, 0 B, 0 E C, 0 F, 1 F B, 0 C, 0 D, 0 13 Let I5=10110, find g(I5,C) and f(I5,C) I5 10 1 1 0 g(I5,C) C B F C B f(I5,C) 1 0 0 1 0 I5 follower of C is F F D Flip-Flop Q

D Positive edge-triggered D Flip-Flop D FF clk C Characteristic equation Q(t+1) = D D Q(t+1) 0 0 1 1 Characteristic Table 14 Timing Diagram of D Flip-Flop Other Flip-Flops D flip-flop is the most common since it requires the fewest number of gates to construct. Two other widely used flip-flops JK flip-flops T flip-flops JK flip-flops Three FF operations 1. Set 2. Reset 3. Complement 16 JK Flip-Flops Q J C K J K Q(t+1) next state 0 0

Q(t) no change 0 1 0 Reset 1 0 1 Set 1 1 Q(t) Complemen t Characteristic Table Characteristic equation Q(t+1) = JQ(t) + KQ(t) 17 T (Toggle) Flip-Flop Complementing flip-flop Q T C T Q(t+1) next state 0 Q(t) no change 1 Q(t) Complemen t Characteristic Table

Characteristic equation Q(t+1) = T Q J C T Q D C K 18 Characteristic Equations The logical properties of a flip-flop can be expressed algebraically using characteristic equations D flip-flop Q(t+1) = D JK flip-flop Q(t+1) = JQ(t) + KQ(t) T flip-flop Q(t+1) = Q(t) T 19 What if we have Q(t+1) and Q(t), and looking for J and K values? Q(t)Q(t+1) 00 01 11 10 0,X 1,X X,0 X,1 J,K 20 J= Q(t+1) Q(t)=0 X Q(t)=1 K= Q(t+1) Q(t)=1 X Q(t)=0 What if we have Q(t+1) and Q(t), and looking for D value? Q(t)Q(t+1) 00 01 11 10 0 1 1 0

21 D= Q(t+1) What if we have Q(t+1) and Q(t), and looking for T value? Q(t)Q(t+1) 00 01 11 10 0 1 0 1 22 T= Q(t+1) Q(t) Asynchronous Inputs of Flip-Flops They are used to force the flip-flop to a particular state independent of clock Preset (direct set) set FF state to 1 Clear (direct reset) set FF state to 0 They are especially useful at startup. In digital circuits when the power is turned on, the state of flip-flops are unknown. Asynchronous inputs are used to bring all flip-flops to a known starting state prior to clock operation. 23 Asynchronous Inputs data Q D clk C D R Q reset reset reset C D Q Q 1 X

X 0 1 0 0 0 1 0 1 1 0 Starting State 24 Analysis of Clocked Sequential Circuits Goal: to determine the behavior of clocked sequential circuits Behavior is determined from Inputs Outputs State of the flip-flops We have to obtain Boolean expressions for output and next state output & state equations (state) table (state) diagram 25 Analyze the circuit Run it and check the timing diagram State Equations Also known as transition equations specify the next state as a function of the present state and inputs Example A(t+1) x A Q D C

B(t+1) A B Q D C B y clk 28 Output and State Equations A(t+1) = B(t+1) = y= A(t+1) x A Q D C B(t+1) A B Q D C B y clk 29 Flip Flop Input Equations Flip-Flop input (excitation) equations Same as the state equations in D flip-flops 30 Example: State (Transition) Table y= A(t+1) =

B(t+1) = Present state input Next state output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 1

0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 1 A sequential circuit with m FFs and n inputs needs 2m+n rows in the transition table 31 Example: State Diagram Present state 1/1 0/0 0/0

00 1/0 0/0 0/0 01 11 1/0 input Next state output A B x A B y 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0

0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 1

10 1/0 What is this circuit doing? State diagram provides the same information as state table 32 Analysis with JK Flip-Flops For a D flip-flop, the state equation is the same as the flip-flop input equation Q(t+1) = D For JK flip-flops, situation is different Goal is to find state equations Method 1. determine flip-flop input equations 2. List the binary values of each input equation 3. Use the corresponding flip-flop characteristic table to determine the next state values in the state table 33 Example: Analysis with JK FFs JA x KA JB J Q A Q Q B C K JD clk CC 1 K KB y Flip-flop input equations JA = JB = and KA = and KB =

34 Example: Analysis with JK FFs JA = Bx and KA = x+B JB = x and KB = 1 present State input next state FF inputs A B x A B JA KA JB KB 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0

1 1 0 1 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1

1 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 35 Example: Analysis with JK FFs Characteristic equations A(t+1) = JAA + KAA B(t+1) = JBB + KBB Input equations JA = Bx and KA = x+B JB = x and KB = 1 State equations A(t+1) = B(t+1) = =

36 State Diagram 1/1 0/0 0/0 00 1/0 0/0 0/0 11 1/0 01 10 Present state input Next state output A B x A B y 0 0 0 0 0 0 0 0 1

0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0

1 1 1 0 0 1 1/0 What is the circuit doing? 37 Analysis with T Flip-Flops Method is the same Example TA = TB = TA x Q T A y1 C TB Q Q TD clk CC y0 B y1 = A reset y0 = B 38 Example: Analysis with T Flip-Flops Characteristic equation A(t+1) = TA A B(t+1) = TB B Input equations TA = xB TB = x

Output equations y1 = A y0 = B State equations A(t+1) = B(t+1) = 39 State Table & Diagram A(t+1) = xB A B(t+1) = x B y1 = A; y0 = B Present state inpu t A B x 0 Next state A B 00/00 output y1 0 1 y0 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 11/11 0 01/01 1 10/10 0 40 Mealy and Moore Models There are two models for sequential circuits Mealy Moore They differ in the way the outputs are generated Mealy: output is a function of both present states and inputs Moore output is a function of present state only 41 Example: Mealy and Moore Machines x y Q D

clock C C reset S Mealy machine External inputs, x and y, are asynchronous Thus, outputs may have momentary (incorrect) values Inputs must be synchronized with clocks Outputs must be sampled only during clock edges 42 Example: Moore Machines x Q T A y C Q Q TD clk CC B reset Outputs are already synchronized with clock. They change synchronously with the clock edge. 43 Design Example - 1 Implement the following state diagram with D FFs. 1/0 0/0 1/1 1 0 0/1 44

Design Example - 1 Implement the following state diagram with D FFs. x 1/0 0/0 1 0 0/1 45 1/1 Q(t) Q(t+1) 0 0 0 1 1 0 1 1 D Z Design Example - 1 Implement the following state diagram with D FFs. x 1/0 0/0 1 0 0/1 46 1/1 Q(t) Q(t+1) D Z 0

0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Design Example - 1 Implement the following state diagram with D FFs. x 1/0 0/0 1 0 1/1 0/1 x clk D 47 Q Z Q(t) Q(t+1) D Z 0

0 0 0 0 0 1 0 0 1 1 0 1 1 0 1 1 1 1 1 Design Example - 2 Design a sequential circuit that counts up (00, 01, 10, 11,00,) when x=1, and counts down (00,11,10,01,00,) when x=0. Use JK FFs. 48 Design Example - 2 Design a sequential circuit that counts up (00, 01, 10, 11,00,) when x=1, and counts down (00,11,10,01,00, ) when x=0. Use JK FFs. 49 x=1 00 01 x=1

x=0 x=1 10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 50 KA JB

KB x=1 00 01 x=1 x=0 x=1 10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 0 1 X 0 1 1 1 0 X 1 0 0 0 1 0 1 0 1 1 0

1 1 1 0 1 1 X 1 1 1 0 0 X KA J= Q(t+1) Q(t)=0 X Q(t)=1 K= Q(t+1) Q(t)=1 X Q(t)=0 51 JB KB x=1 00 01 x=1 x=0 x=1 10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA KA 0 0 0 1 1

1 X 0 0 1 0 0 0 X 0 1 0 0 1 X 1 0 1 1 1 0 X 0 1 0 0 0 1 0 X 1 0 1 1 0 1 X 1 1 0 1 1 X 0

1 1 1 0 0 X 1 J= Q(t+1) Q(t)=0 X Q(t)=1 K= Q(t+1) Q(t)=1 X Q(t)=0 52 JB KB x=1 00 01 x=1 x=0 x=1 10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA KA JB 0 0 0 1 1 1 X 1 0 0 1

0 0 0 X X 0 1 0 0 1 X 1 1 0 1 1 1 0 X 0 X 1 0 0 0 1 0 X 1 1 0 1 1 0 1 X X 1 1 0 1 1 X

0 1 1 1 1 0 0 X 1 X J= Q(t+1) Q(t)=0 X Q(t)=1 K= Q(t+1) Q(t)=1 X Q(t)=0 53 KB x=1 00 01 x=1 x=0 x=1 10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA KA JB KB 0 0 0 1 1 1

X 1 X 0 0 1 0 0 0 X X 1 0 1 0 0 1 X 1 1 X 0 1 1 1 0 X 0 X 1 1 0 0 0 1 0 X 1 X 1 0 1

1 0 1 X X 1 1 1 0 1 1 X 0 1 X 1 1 1 0 0 X 1 X 1 J= Q(t+1) Q(t)=0 X Q(t)=1 K= Q(t+1) Q(t)=1 X Q(t)=0 54 x=1 00 01 x=1 x=0 x=1

10 11 x=1 Design Example - 2 x A B A(t+1) B(t+1) JA KA JB KB 0 0 0 1 1 1 X 1 X 0 0 1 0 0 0 X X 1 0 1 0 0 1 X 1 1 X 0 1 1 1 0 X 0

X 1 1 0 0 0 1 0 X 1 X 1 0 1 1 0 1 X X 1 1 1 0 1 1 X 0 1 X 1 1 1 0 0 X 1 X 1 AB x x=1

00 01 x=1 10 11 x=1 AB 00 01 11 10 0 1 0 X X 1 0 1 X X 55 x x=1 x=0 00 01 11 10 0 X X 0

1 1 X X 1 0 Design Example - 2 JA=xB+xB KA=xB+xB JB=1 KB=1 Draw the circuit 56 Design Example - 3 57 Design Example - 3 000 58 001 010 011 100 101 Design Example - 3 A(t) 0 0 0 0 1 1 B(t) 0 0 1 1 0 0 J=

C(t) 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 Q(t+1) Q(t)=0 X Q(t)=1 000

59 001 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 JA KA JB KB Q(t+1) Q(t)=1 X Q(t)=0 K= 010 z6 0 0 0 1 0 0 011 100 101 JC KC Design Example - 3 A(t) 0 0 0 0 1 1 B(t) 0

0 1 1 0 0 J= C(t) 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1

Q(t+1) Q(t)=0 X Q(t)=1 000 60 001 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 JA 0 0 0 1 KA JB 0 1 KB 011 0 0 100 JC 1 1 1 Q(t+1) Q(t)=1 X Q(t)=0 K= 010 z6 0 0 0

1 0 0 101 KC Design Example - 3 A(t) 0 0 0 0 1 1 B(t) 0 0 1 1 0 0 J= C(t) 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0

0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 Q(t+1) Q(t)=0 X Q(t)=1 000 61 001 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 JA 0 0 0 1 X X KA JB 0 1 X X 0 0 KB

Q(t+1) Q(t)=1 X Q(t)=0 K= 010 z6 0 0 0 1 0 0 011 100 101 JC 1 X 1 X 1 X KC Design Example - 3 A(t) 0 0 0 0 1 1 B(t) 0 0 1 1 0 0 J= C(t) 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1

0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 Q(t+1) Q(t)=0 X Q(t)=1 000 62 001 z4 0 1 1 1 1 1 z5 0

0 1 1 1 0 JA 0 0 0 1 X X KA 0 1 JB 0 1 X X 0 0 KB 0 1 Q(t+1) Q(t)=1 X Q(t)=0 K= 010 z6 0 0 0 1 0 0 011 100 101 JC 1 X 1 X 1 X KC 1 1

1 Design Example - 3 A(t) 0 0 0 0 1 1 B(t) 0 0 1 1 0 0 J= C(t) 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1

0 0 0 1 z3 1 1 1 0 1 1 Q(t+1) Q(t)=0 X Q(t)=1 000 63 001 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 JA 0 0 0 1 X X KA X X X X 0 1 JB 0 1 X X 0 0 KB

X X 0 1 X X Q(t+1) Q(t)=1 X Q(t)=0 K= 010 z6 0 0 0 1 0 0 011 100 101 JC 1 X 1 X 1 X KC X 1 X 1 X 1 Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1

C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 BC A 00 01 11 0 0 0 1 X X 1 0 0 0 0 0

z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 z6 0 0 0 1 0 0 JA 0 0 0 1 X X X X KA X X X X 0 1 X X JB 0 1 X X

0 0 X X KB X X 0 1 X X X X JC 1 X 1 X 1 X X X KC X 1 X 1 X 1 X X 10 BC A 00 01 11 10 1 0 0 X X X X X X

1 0 1 X X JA=BC64 KA=C Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1 C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0

1 0 1 0 1 0 BC A 00 01 11 0 0 1 1 0 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 z4 0 1 1 1 1 1 z5 0 0 1 1 1

0 z6 0 0 0 1 0 0 JA 0 0 0 1 X X X X KA X X X X 0 1 X X JB 0 1 X X 0 0 X X KB X X 0 1 X X X X JC 1 X 1 X 1 X X X KC X 1 X 1

X 1 X X 10 BC A 00 01 11 10 X X 0 X X 1 0 X X 1 X X X X JB=AC65 KB=C Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1

1 0 0 1 1 C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 BC A 00 01 11 0 1 X 1 1 X 1 0

0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 z6 0 0 0 1 0 0 JA 0 0 0 1 X X X X KA X X X X 0 1 X X

JB 0 1 X X 0 0 X X KB X X 0 1 X X X X JC 1 X 1 X 1 X X X KC X 1 X 1 X 1 X X 10 BC A 00 01 11 10 1 X 0 X 1 1

X X X 1 X 1 X X JC=1 66 KC=1 Design Example - 3 JA QA C JB C KA KB 67 QB JC C KC QC Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1

C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 z4 0 1 1 1

1 1 z5 0 0 1 1 1 0 z6 0 0 0 1 0 0 JA 0 0 0 1 0 0 0 1 KA 0 1 0 1 0 1 0 1 JB 0 1 0 1 0 0 0 0 KB 0 1 0 1 0 1 0 1 JA=BC KA=C JB=AC

KB=C JC=1 KC=1 68 JC 1 1 1 1 1 1 1 1 KC 1 1 1 1 1 1 1 1 Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1 C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0

0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 z6

0 0 0 1 0 0 JA 0 0 0 1 0 0 0 1 KA 0 1 0 1 0 1 0 1 JB 0 1 0 1 0 0 0 0 KB 0 1 0 1 0 1 0 1 JA=BC A(t+1)=BCA+CA KA=C JB=AC B(t+1)=ACB+CB C(t+1)=C KB=C JC=1 69 KC=1

JC 1 1 1 1 1 1 1 1 KC 1 1 1 1 1 1 1 1 Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1 C(t) 0 1 0 1 0 1 0 1 A B C (t+1) (t+1) (t+1) z1 0 0 0 1 1 0 1 0

0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 000 001 111 110 70 1 0 0 0 0 0 z2 1 1 0 0 0 1 z3 1 1 1 0 1 1 010 z4 0 1 1 1 1 1 z5 0 0 1 1

1 0 011 z6 0 0 0 1 0 0 JA 0 0 0 1 0 0 0 1 KA 0 1 0 1 0 1 0 1 100 JB 0 1 0 1 0 0 0 0 KB 0 1 0 1 0 1 0 1 101 JC 1 1 1 1 1 1 1

1 KC 1 1 1 1 1 1 1 1 Design Example - 3 Repeat your design with D FFs 71 Design Example - 3 A(t) 0 0 0 0 1 1 1 1 B(t) 0 0 1 1 0 0 1 1 A B C C(t) (t+1) (t+1) (t+1) 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 z1 1 0 0 0 0 0 z2 1 1 0 0

0 1 z3 1 1 1 0 1 1 z4 0 1 1 1 1 1 z5 0 0 1 1 1 0 z6 DA DB DC 0 1 0 1 0 1 1 1 1 0 1 1 0 1 1 1 A(t+1)=BCA+CA = DA B(t+1)=ACB+CB = DB C(t+1)=C = DC 72 Design Example - 4 Design a logic circuit that detects the sequence 1011 and outputs 1 in that case, 0 otherwise. 73 Design Example - 4 1/1 0/0 1/0 0/0 I.C. 1 1/0

10 101 0/0 1/0 0/0 74 Design Example - 4 1/1 0/0 1/0 0/0 00 01 1/0 10 11 0/0 1/0 0/0 75 Design Example - 4 x(t) A(t) B(t) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 76 A B

(t+1) (t+1) 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 Z 0 0 0 0 0 0 0 1 JA KA JB KB Design Example - 4 x(t) A(t) B(t) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 77

A B (t+1) (t+1) 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 Z JA KA JB KB 0 0 0 0 0 0 0 1 0 1 X X 0 0 X X X X 1 0 X X 0 1 0 X 0 X 1 X 1

X X 1 X 1 X 0 X 0 Design Example - 4 AB x AB 00 01 11 10 0 0 1 X X 1 0 0 X X x 00 01 11 10 0 X X 0 1 1

X X 1 0 JA=xB KA=xB+xB AB x AB 00 01 11 10 0 0 X X 0 1 1 X X 1 JB=x 78 x 00 01 11 10 0 X 1 1

X 1 X 0 0 X KB=x Design Example - 4 JA C KA 79 QA JB C KB QB Design Example - 4 DA C 80 QA DB C QB

## Recently Viewed Presentations

• Box Plot (formerly known as box and whisker) If you have a large set of data, and want to present how the data cluster you may use a box plot. The box plot displays the median, the quartiles and outlier...
• Prof. Thomas Sterling Prof. Hartmut Kaiser Department of Computer Science Louisiana State University April 12th, 2011 HIGH PERFORMANCE COMPUTING: MODELS, METHODS, & MEANS
• A zero of a function is a value of the input x that makes the output f(x) equal zero.The zeros of a function are the x-intercepts.. Unlike linear functions, which have no more than one zero, quadratic functions can have...
• Marine Biome Summer Martin February 13th, 2009 Map Longitude and Latitude Antarctic Ocean - 65 00 S, 0 00 E Arctic Ocean - 90 00 N, 0 00 E Indian Ocean - 20 00 S, 80 00 E Atlantic Ocean...
• iissa. integrated holistic education system (ihes) and its application in . qur'anic generation development . for fikrah session. prepared by : hasni mohammed
• Why do auditors ask for GR&R studies? Why is MSA regarded as GR&R? Are (some) Customers leading the thinking? Why is MSA limited to products? Do you know your Customer expectations? Do organisations, auditors, quality mangers understand? MSA, ANOVA, crossed...
• A politico tries to keep everyone happy and thus is a true politician. The Role of Legislators The Role of Legislators How members of Congress vote and how they view their role as law makers Four Roles: Delegate Partisan Trustee...
• Yazı, dış belleği mümkün kılar, kaydedilen haber ve bilgilerin canlanıp beklenmedik ölçüde yaygınlaşmasını sağlar. Yazı, aynı zamanda doğal belleğin kapasitesinin kullanımını azaltır. Bellek Bellek konusunda bir başka ayrım Paul Connerton (1999) tarafından yapılır.