Versatile board to study the in-orbit radiation effects on microelectronics components MAPLD 2009 31th August-3rd September David Guzmn1, Manuel Prieto1, Javier Almena1, J. Ignacio Garca, Vctor Ruz1, Sebastin Snchez1, Daniel Meziat1, Oleksiy Dudnik2 {dguzman, mpm, jalmena, nach, vruiz, chan, meziat}@srg.aut.uah.es, [email protected] Space Research Group, University of Alcal, Spain 2 Space Research Section. Physics and Technics Department. Kharkiv University. Ukraine 1 Agenda Introduce Space Research Group (SRG) SIDRA Project Overview
aDUT board Motivations Architecture Reliability Features System Testing Conclusions and future work 2 Space Research Group University of Alcala, Spain. http://www.srg.uah.es Two divisions: Scientific, Department of Physics Technical, Computer Engineering Department
Capabilities: Solar Physics research Mission planning and ground systems Test development tools On board software development On board electronics development 3 Space Research Group Projects Finished: SOHO: CDPU CEPAC consortium PHOTON: PESCA Instrument FUEGO 2: OBDH and flight software NanoSat 01/B: flight software and maintenance ExoMars: Autonomous Navigation Software Porting to RTEMS LEON2 platform
In progress: MicroSat: OBDH, RTUs, MMU, EGSE and flight software SIDRA: DPU, DUT, ADUT Solar Orbiter: LVPS and CDPU for EPD experiment 4 SIDRA Project What is SIDRA? Space Instrument for Determination of digital microelectronic components RAdiation tolerance Investigation of single event efects (SEE) Measurement of energetic charge particle, fluxes and total absorbed doses The project is leaded by the Physics and Technics Department of the
Kharkiv National University (Ukraine) International Partners: Space Research Group of the University of Alcal (Spain) Space Research Laboratory of the University of Turku (Finland) 5 Block diagram of SIDRA instrument 2 silicon PIN detectors SRAM Scintillator detector SDRAM
Amplification and shaping electronics SoC based on 32 bit SPARC V8 LEON2 Fast ADCs 6 General view of SIDRA instrument 7
aDUT motivations Main features of the DUT board The DPU directly interfaces the DUT board through the main system bus. Fixed types of memory chips A solution is required to add versatility to the DUT!! The answer is aDUT with the following key elements Board based on an FPGA (Actel A3P600) Simple proccesing capability JTAG interface AMBA bus 8
Work in Progress !! aDUT architecture The aDUT FPGA implements a SoC AMBA bus JTAG block AMBA interface TAP controller Memory controller Embedded RAM Watchdog Block 10 Realibility Features
Due to the criticality of the AMBA bus and the JTAG interface, in the aDUT architecture: Built-in Self-Test ensuring the device integrity Watchdog timer. Flip-flops are triplicated according to the Triple Modular Redundancy scheme. 11 Implementation details Results obtained to resources consumption of the A3P600 FPGA Type of resource Used
Core 2432 out of 13824 17,59 % IO (W/clocks) 101 out of 270 37,47 % Global (Chip + Quadrant) 3 out of 18 16,67 RAM/FIFO
4 out of 8 16,67% USER JTAG 1 out of 1 100% 12 JTAG Command Generator This new block is included in the DPU Allows the communication between the DPU and the aDUT board through the JTAG interface Acts as master in the JTAG base command-response protocol, performing read/write operations into the memory chips contained in
the aDUT board Commands: Responses: aDUT_c_Ping aDUT_r_ACK aDUT_c_Write aDUT_r_FAIL aDUT_c_Read
aDUT_r_Data aDUT_c_Memory_Test 13 System Testing (I) ProASIC3 Starter Kit from Actel aDUT SoC Aeroflex Gaisler/Pender XC3S-1500 DPU + JTAG Command Generator JTAG clock 1 MHz (tck)
We expect to end the board manufacturing this month Planned to go to Jyvaskyla accelerator (Finland) in December 14 Conclusions A board based on FPGA and designed to test the in-orbit radiation effects on different microelectronic was presented The design is based on mature and validated architectures AMBA JTAG Its modular design allows the easy integration of new memory types, such as DDR and FLASH memories The design is optimized for the selected FPGA family but can be quickly migrated to other FPGA devices
The small sized allows an easy integration in more complex systems The aDUT concept can be used as massive memory unit only by increasing the number of memory chips and changing the JTAG interface for high rate protocols such as Spacewire 15 ACKNOWLEDGMENTS This work has been supported by: CAM/UAH (Ref. CCG08-UAH/ESP-3991) CICYT (grant ESP2005-07290-C02-02) 16 References Dudnik Oleksiy, Meziat Daniel, Prieto Manuel. The concept of compact on-board
instrument for measurements of particle fluxes & dose rates. Scientific session MEPHI-2009, Abstracts of reports, Vol. No.2 , P. 151. Prieto Manuel, Guzmn David, Garca Jos Ignacio, Parra Pablo, Knoblauch Martin, Snchez Sebastin, Meziat Daniel, Dudnik Oleksiy, Bilogub Vladimir. Unidad de Control del instrumento cientfico SIDRA. Reconfigurable Computing and Applications Conference 2009. Gaisler Research. LEON2 Processor Users Manual. 2005. http://www.gaisler.com Institute of Electrical and Electronics Engineers, Inc. IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1- 1990). New York: Institute of Electrical and Electronics Engineers, Inc., 1990. AMBA Specification Rev 2.0 2007. http://www.arm.com 17
