Photo Album - Milwaukee School of Engineering

Photo Album - Milwaukee School of Engineering

Flash Storage and IO Operation Lecture Objectives: 1) 2) 3) 4) 5) Explain the limitations of flash memory. Define wear leveling. Define the term IO Transaction Define the terms synchronous bus and asynchronous interconnect.

Explain the difference between polling and interrupts Nonvolatile semiconductor storage 100 1000 faster than disk Smaller, lower power, more robust But more $/GB (between disk and DRAM) Chapter 6 Storage and Other I/O Topics 2 6.4 Flash Storage Flash Storage

Flash Memory Performance Limitations Cost is higher than mechanical drives Cells wear out over time CS2710 Computer Organization 3 Flash memory can only be written to a finite number of times Write operations begin to fail after 10000100000 cycles (current technology)

Disk drives or DRAM memory do not have this limitation Wear leveling A technique which organizes blocks of data so that blocks which have been rewritten many times are exchanged for blocks which have not been written as often. CS2710 Computer Organization 4 CS2710 Computer Organization

5 Definitions Processor memory bus A bus that connect the processor to the memory, and is generally high speed. Backplane bus A bus that is designed to allow processors, memory, and I/O devices to coexist on a single bus IO Transaction

A sequence of operations over the interconnect that includes a request, and may include a response either of which may carry data. Synchronous bus A bus that includes clock and control lines and a fixed protocol for communicating that is relative to the clock Asynchronous interconnect A mechanism which uses a handshaking protocol rather than a clock to accommodate devices of varying speeds. CS2710 Computer Organization 6

I/O is mediated by the OS Multiple programs share I/O resources Need protection and scheduling I/O causes asynchronous interrupts Same mechanism as exceptions I/O programming is fiddly OS provides abstractions to programs 6.6 Interfacing I/O Devices

I/O Management I/O Commands I/O devices are managed by I/O controller hardware Transfers data to/from device Synchronizes operations with software Command registers Cause device to do something Status registers Indicate what the device is doing and occurrence of errors

Data registers Write: transfer data to a device Read: transfer data from a device I/O Register Mapping Memory mapped I/O Registers are addressed in same space as memory Address decoder distinguishes between them OS uses address translation mechanism to make them only accessible to kernel I/O instructions Separate instructions to access I/O registers

Can only be executed in kernel mode Example: x86 Polling Interrupts -> Part #1 10 Polling Periodically check I/O status register If device ready, do operation If error, take action

Common in small or low-performance realtime embedded systems Predictable timing Low hardware cost In other systems, wastes CPU time Chapter 6 Storage and Other I/O Topics 11 Interrupts No! Shut up and Ill tell you when we are there!

Interrupts -> Part #1 12 Interrupts When a device is ready or error occurs Controller interrupts CPU Interrupt is like an exception But not synchronized to instruction execution Can invoke handler between instructions

Cause information often identifies the interrupting device Priority interrupts Devices needing more urgent attention get higher priority Can interrupt handler for a lower priority interrupt Chapter 6 Storage and Other I/O Topics 13

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