Lecture 2 - University of Central Florida

Lecture 2 - University of Central Florida

Lecture 2 Interrupt Handling by Euripides Montagne University of Central Florida Outline 1. The structure of a tiny computer. 2. A program as an isolated system. 3. The interrupt mechanism. 4. The hardware/software interface. 5. Interrupt Types. Eurpides Montagne University of Central Florida 2 Von-Neumann Machine (VN) PC

MAR MEMORY IR OP ADDRESS MDR A Decoder ALU Eurpides Montagne University of Central Florida 3 Instruction Cycle

Instruction cycle, or machine cycle, in VN is composed of 2 steps: 1. Fetch Cycle: instructions are retrieved from memory 2. Execution Cycle: instructions are executed A hardware description language will be used to understand how instructions are executed in VN Eurpides Montagne University of Central Florida 4 Definitions PC: Instruction Pointer is a register that holds the address of the next instruction to be executed. MAR: Memory Address Register is used to locate a specific memory location to read or write its content. MEM: Main storage, or RAM (Random Access Memory) and is used to store programs and data.

Eurpides Montagne University of Central Florida 5 Definition of MDR MDR: Memory Data Register is a bi-directional register used to receive the content of the memory location addressed by MAR or to store a value in a memory location addressed by MAR. This register receives either instructions or data from memory Eurpides Montagne University of Central Florida 6 Definitions Cont. IR: Instruction Register is used to store instructions

DECODER: Depending on the value of the IR, this device will send signals through the appropriate lines to execute an instruction. A: Accumulator is used to store data to be used as input to the ALU. ALU: Arithmetic Logic Unit is used to execute mathematical instructions such as ADD, or MULTIPLY Eurpides Montagne University of Central Florida 7 Fetch Execute Cycle In VN, the instruction cycle is given by the following loop: Fetch Execute In order to explain further details about the fetch /execute cycle, the data movements along different paths can be described in 4 steps.

Eurpides Montagne University of Central Florida 8 Data Movement 1 PC Given register PC and MAR the transfer of the contents of PC into MAR is indicated as : MARPC MAR MEMORY OP ADDRESS

MDR A Decoder ALU Eurpides Montagne University of Central Florida 9 Data Movement 2 To transfer information from a memory location to the register MDR, we use: PC MAR MEMORY

MAR MDRMEM[MAR] The address of the memory location has been stored previously into the MAR register OP ADDRESS MDR A Decoder ALU Eurpides Montagne University of Central Florida

10 Data Movement 3 To transfer information from the MDR register to a memory location, we use: MEM [MAR] MDR *see previous slide for diagram The address of the memory location has been previously stored into the MAR Eurpides Montagne University of Central Florida 11 Instruction Register Properties The Instruction Register (IR) has two fields: Operation (OP) and the ADDRESS. These fields can be accessed using the selector operator .

Eurpides Montagne University of Central Florida 12 Data Movement 4 The operation field of the IR register is sent to the DECODER as: DECODERIR.OP The Operation portion of the field is accessed as IR.OP DECODER: If the value of IR.OP==0, then the decoder can be set to execute the fetch cycle again. Eurpides Montagne University of Central Florida 13 Data Movement 4 Cont.

PC DECODERIR.OP MAR MEMORY OP ADDRESS MDR A Decoder ALU Eurpides Montagne University of Central Florida 14

Instruction Cycle The instruction cycle has 2 components. Fetch cycle retrieves the instruction from memory. Execution cycle carries out the instruction loaded previously. Eurpides Montagne University of Central Florida 15 00 Fetch Cycle 1.Copy contents 1.MAR PCof PC into MAR 2. Load content of memory location into MDR 2.MDR MEM[MAR]

3. Copy value stored in MDR into IR 3.IR MDRPC register 4. Increment 5. Select Instruction to be executed 4.PC PC+1 5.DECODER IR.OP Eurpides Montagne University of Central Florida 16 Execution: 01 LOAD 1. 2. 2.

3. 3. 4. 4. Copy IR address value field into MAR MAR the IR.ADDR Load content of a memory location into MDR the MEM[MAR] MDR A MDR Copy content of MDR into A register DECODER 00 Set Decoder to execute Fetch Cycle Eurpides Montagne University of Central Florida

17 Execution: 02 ADD 1. IR address value field into MAR 1. Copy MARtheIR.ADDR 2. Load content of memory location to MDR 2. MDR MEM[MAR] 3. Add contents of MDR and A register and store result into A A + MDR 3. A 4. Set Decoder to execute Fetch cycle 4. DECODER 00 Eurpides Montagne University of Central Florida

18 Execution: 03 STORE 1. 2. 2. 3. 3. Copy IR address value field into MAR MAR the IR.ADDR Copy register contents into MDR MDR A A Copy content MDR of MDR into a memory MEM[MAR]

location 4. DECODER 00 4. Set Decoder to execute fetch cycle Eurpides Montagne University of Central Florida 19 Execution: 04 END 1. Program STOP ends normally Eurpides Montagne University of Central Florida 20 Instruction Set Architecture 00 Fetch (hidden instruction)

MAR PC MDR MEM[MAR] IR MDR PC PC+1 DECODER IR.OP 02 Add MARIR.Address MDR MEM[MAR] A A + MDR DECODER 00 Eurpides Montagne 01 Load MARIR.Address MDR MEM[MAR] A MDR DECODER00 03 Store MARIR.Address MDR A MEM[MAR] MDR DECODER 00

04 Stop University of Central Florida 21 One Address Architecture The instruction format of this one-address architecture is: operation

Address are given in hexadecimal and are preceded by an x, for instance x56 Eurpides Montagne University of Central Florida 22 Example One-Address Program Memory Address x20

450 x21 300 x22 750 (after program execution) x23 Load x24 Add x25 Store x26 End Eurpides Montagne University of Central Florida 23 Programs with Errors So far, we have a computer that can execute programs free from errors. What would happen if an overflow occurred while executing an addition operation?

We need a mechanism to detect this type of event and take appropriate actions. Eurpides Montagne University of Central Florida 24 Overflow Detection A flip/flop will be added to the ALU for detecting overflow The Fetch/Execute cycle has to be extended to: Fetch/Execute/Interrupt cycle. An abnormal end (ABEND) has to be indicated. Eurpides Montagne University of Central Florida 25

VN with Overflow Flip/Flop PC NewPC MAR OldPC MEMORY OP ADDRESS MDR A Decoder ALU OV

Eurpides Montagne University of Central Florida 26 Interrupt Cycle In the interrupt cycle, the CPU has to check for an interrupt each time an instruction is executed. Modifications have to be made to the instruction set to incorporate the interrupt cycle. An operation code of 05 will be added to accommodate the Interrupt Cycle. At the end of each execution cycle, the DECODER will be set to 05 instead of 00, to check for interrupts at the end of each execution cycle. Eurpides Montagne University of Central Florida 27

Interrupt Cycle 05 1. If Abnormal OV=1 End (ABEND) for Overflow 2. SetThen Decoder HALT to Fetch Cycle DECODER 00 Eurpides Montagne University of Central Florida 28 ISA Interrupt cycle 01 Load MARIR.Address MDR MEM[MAR] A MDR DECODER05

02 Add MARIR.Address MDR MEM[MAR] A A + MDR DECODER 05 Eurpides Montagne 03 Store MARIR.Address MDR A MEM[MAR] MDR DECODER 05 04 Stop 05 Abend IF OV = 1 Then HALT DECODER 00 University of Central Florida 29

Interrupt Handling Routine Instead of halting the machine, the flow of execution can be transferred to an interrupt handling routine This is done by loading the PC register with the start address of the interrupt handler in memory from NEWPC. Causes a change in the Interrupt Cycle Eurpides Montagne University of Central Florida 30 Interrupt Handler Takes Control of VN PC NewPC = 0000 MAR

OldPC 0000 MEMORY (INTERRUPT HANDLER) (USER PROGRAM) OP ADDRESS MDR A Decoder ALU OV Eurpides Montagne University of Central Florida

31 05 Interrupt Cycle If Jump OV=1to interrupt handler at memory location 1000 Then PCNEWPC Set decoder to fetch cycle DECODER 00 Eurpides Montagne University of Central Florida 32 Hardware/Software Bridge 01 Load MARIR.Address MDR MEM[MAR] A MDR

DECODER05 02 Add MARIR.Address MDR MEM[MAR] A A + MDR DECODER 05 Eurpides Montagne 03 Store MARIR.Address MDR A MEM[MAR] MDR DECODER 05 04 Stop 05 Interrupt Handler Routine IF OV = 1 PC NEWPC DECODER 00 University of Central Florida 33

Virtual Machine The interrupt handler is the first extension layer or virtual machine developed over VN First step towards an operating system Interrupt Handler VN Interrupt Handler Virtual Machine Eurpides Montagne University of Central Florida 34 Shared Memory The interrupt handler has to be loaded into memory along with any user program. Sharing memory space raises a new problem: the user program might eventually execute an instruction which may modify the interrupt handler routine

Eurpides Montagne University of Central Florida 35 Shared Memory Example Interrupt Handler 3500 4000 User Program Eurpides Montagne Interrupt Handler is loaded at MEM[0] with a length of 4000 words. User program executes:

STORE<3500>, thus modifying the handler routine. University of Central Florida 36 Memory Protection A new mechanism must be implemented in order to protect the interrupt handler routine from user programs. The memory protection mechanism has three components: a fence register, a device to compare addresses, and a flip flop to be set if a memory violation occurs. Eurpides Montagne University of Central Florida 37

Memory Protection Components Fence Register: register loaded with the address of the boundary between the interrupt handler routine and the user program Device for Address Comparisons: compares the fence register with any addresses that the user program attempts to access Flip/Flop: is set to 1 if a memory violation occurs Eurpides Montagne University of Central Florida 38 VN with Memory Protection MP Address < Fence

PC NewPC MAR OldPC MEMORY Fence (4000) OP ADDRESS MDR A Decoder ALU OV

Eurpides Montagne University of Central Florida 39 Changes to the ISA With the inclusion of the mechanism to protect the Interrupt Handler, some modifications need to be made to the ISA (Instruction Set Architecture) Instructions Load, Add, and Store have to be modified to check the value of the Memory Protection (MP) once the first step of those instructions has executed Eurpides Montagne University of Central Florida 40 Modified ISA

01 03 Load Store MARIR.Address MARIR.Address If MP=0 Then If MP=0 MDRThen MEM[MAR] MDR A A MDR MEM[MAR] DECODER 05 MDR Decoder 05 02 05 Add Interrupt Handler Routine MARIR.Address IF OV = 1 PC NEWPC

If IFMP=0 MP = 1Then PC NEWPC MDR MEM[MAR] DECODER 00 A A + MDR DECODER 05 Eurpides Montagne University of Central Florida 41 Program State Word (PSW) The PSW, or Program State Word, is a structure that give us information about the state of a program. In this register, we have the PC, MODE, Interrupt Flags, and the Mask(defined later) Eurpides Montagne

University of Central Florida 42 Program State Word Interrupt Flags PC OV MP Eurpides Montagne MASK To be defined later University of Central Florida

43 Privileged Instructions What if a user program attempted to modify the fence register? The register is not protected so it does not fall under the previous memory protection mechanism. Use the idea of privileged instructions to denote which instructions are prohibited to user programs Eurpides Montagne University of Central Florida 44 Privileged Instruction Implementation To distinguish between times when privileged instructions either are or are not allowed, the

computer operates in two modes User mode: 0 Supervisor mode: 1 From now on, interrupt handler and supervisor are terms that can be used interchangeably In User mode, only a subset of the instruction set can be used The supervisor has access to all instructions Eurpides Montagne University of Central Florida 45 Implementing Privileged Instructions cont. 1. Add another flip/flop (flag) to the CPU and denote it as the mode bit 2. Create a mechanism in the CPU to avoid the execution of privileged instructions by user programs 3. The instruction set has to be organized in such a

way that all privileged instructions have operation codes greater than a given number. -For example, if the ISA has 120 instructions, privileged instructions will have operation codes greater than 59 University of Central Florida Eurpides Montagne 46 Mechanism for User/Supervisor Modes This device compares the opcode in the Instruction Register (IR.OP) with the opcode of the last non-privileged instruction. If the outcome yields a 1, then this is a privileged instruction. This outcome is then compared with the mode bit. If the mode is 0 (indicating user mode), and it is a privileged instruction, then the Privileged Instruction bit (PI) is set to one. The hardware will detect the event, and the interrupt handler routine will be executed Eurpides Montagne

University of Central Florida 47 Mechanism for User/Supervisor Modes Cont. IR.OP 59 Mode Bit = 0 > PI Eurpides Montagne University of Central Florida 48

CPU After Mode Flag Addition CPU PC NewPC OV MP PI Mode Fence Accumulator Eurpides Montagne Supervisor Mode PSW

User Mode University of Central Florida 49 PSW After Mode and PI flag Addition Interrupt Flags PC MASK Mode OV MP Eurpides Montagne

PI To be defined later University of Central Florida 50 Types of Interrupts Traps Software Interrupts Interrupts Hardware Interrupts External Eurpides Montagne System Calls

I/O Interrupt Timer University of Central Florida 51 Traps An interrupt is an exceptional event that is automatically handled by the interrupt handler. In the case of an overflow, memory addressing violation, and the use of privileged instruction in user mode, the handler will abort the program These types of interrupts are called traps All traps are going to be considered synchronous interrupts Eurpides Montagne University of Central Florida 52

I/O Interrupts This type of interrupt occurs when a device sends a signal to inform the CPU that an I/O operation has been completed An I/O flag is used to handle this type of interrupt When an I/O interrupt occurs, the Program State of the running program is saved so that it can be restarted from the same point after the interrupt has been handled. Eurpides Montagne University of Central Florida 53 Saving the state of the running program MP Address < Fence

PC NewPC MAR OldPC MEMORY Fence (4000) OP ADDRESS MDR A Decoder ALU

OV Eurpides Montagne University of Central Florida 54 Program State Word Interrupt Flags PC MASK Mode OV MP PI I/O

To be defined later I/O Device Eurpides Montagne University of Central Florida 55 05 Interrupt Cycle IF OV = 1 THEN PC NEWPC; MODE 1 (ABEND). IF MP = 1 THEN PC NEWPC; MODE 1 (ABEND). IF PI = 1 THEN PC NEWPC; MODE 1 (ABEND) IF I/O = 1 THEN OLDPC PC; PC NEWPC; MODE1; DECODER 00 Eurpides Montagne

University of Central Florida 56 Supervisor The Supervisor can use both user and privileged instructions. Sometimes a user program requires some services from the Supervisor, such as opening and reading files. A program cannot execute open or read functions itself, and therefore a mechanism to communicate with the Supervisor is required Eurpides Montagne University of Central Florida 57 SuperVisorCall (SVC)

An SVC is also known as a System Call It is a mechanism to request service from the Supervisor or OS. This mechanism is a type of interrupt, called a software interrupt because the program itself relinquishes control to the Supervisor as part of its instructions. Eurpides Montagne University of Central Florida 58 System Calls There are two types of system calls: 1. Allows user programs to ask for service (instructions found below opcode 59) 2. Privileged Instructions (over opcode 59) Eurpides Montagne University of Central Florida

59 SCVT The System Call Vector Table(SCVT) contains a different memory address location for the beginning of each service call Service calls are actually programs because they require multiple instructions to execute Each memory address contained in the SCVT points to runtime library, generally written in assembly language, which contains instructions to execute the call Eurpides Montagne University of Central Florida 60 Runtime Libraries Runtime Libraries: precompiled procedures that can be called at runtime

Runtime Libraries set a new flip/flop, called the SVC flag, to 1, which causes the system to switch to Supervisor Mode in the Interrupt Cycle Eurpides Montagne University of Central Florida 61 Properties of Runtime Libraries Libraries are shared by all programs Are not allowed to be modified by any program. Eurpides Montagne University of Central Florida 62

SVC Instruction Format SVC(index) is the format for system calls. The index is the entry point in the SCVT Read SVC(index) (IR.OP=SVC, IR.ADDR=index) Compiler Eurpides Montagne University of Central Florida 63 80 SVC(index) 80 SVC(index) Save PC of current program OLDPCPC; The Index value is temporarily loaded into register B B IR.ADDRESS Address

of Runtime Library Transfer to Interrupt Cycle PC RTL-ADDRESS DECODER 05 Eurpides Montagne University of Central Florida 64 SVC(read) = 80(4) PC MP NewPC 1 MAR

Address < Fence 3 MEMORY RTL-Address 2 Fence (4000) OP ADDRESS OldPC MDR B

A Decoder ALU OV Eurpides Montagne University of Central Florida 65 Runtime Library and SVCT Example Runtime Library for Read User Program SVC(4) -

------------------------------------------SVCFLAG=1 ------------------------------------------LOADPC OLD-PC Address Open Address Close Address Write 1 2 3 Eurpides Montagne Address Read

4 Address End 5 University of Central Florida I.H. searching code for Read IF SVCFLAG=1 PC SCVT[B] -------------------------------------------------------LOADPC OLD-PC SCVT 66 The PC is overwritten!!! User Program SVC(4) -

Runtime Library for Read ------------------------------------------SVCFLAG=1 ------------------------------------------LOADPC OLD-PC When SVC(4) is executed OLDPC PC and after executing SVCFLAG = 1, OLDPC PC in the interrupt cycle. Eurpides Montagne University of Central Florida I.H. searching code for Read IF SVCFLAG=1 PC SCVT[B] -------------------------------------------------------LOADPC OLD-PC 67 80 SVC(index) 80 SVC(index) Save PC of current program

OLDPCPC; The Index value is temporarily loaded into register B B IR.ADDRESS Address of Runtime Library Transfer to Interrupt Cycle PC RTL-ADDRESS DECODER 05 Eurpides Montagne University of Central Florida 68 05 Interrupt Cycle If OV=1 Then PC NEWPC; MODE 1 (ABEND) If MP=1 Then PC NEWPC; MODE 1 (ABEND) If PI=1 Then PC NEWPC; MODE 1 (ABEND) IF I/O = 1 THEN OLDPC PC;

PC NEWPC; MODE1 ; If SVC=1, THEN OLDPC PC; PC NEWPC; MODE 1; DECODER 00 Eurpides Montagne University of Central Florida 69 How can we handle nested interrupts? Introducing the concept of a Stack. 1.- The OLDPC register is used as an stack pointer 2.- OLDPC register will be rename Stack Pointer (SP) Eurpides Montagne University of Central Florida

70 The Stack will store all return addresses PC NewPC 1 MP 2 MAR Address < Fence RTL-Address

MEMORY SP stack 3 Fence (4000) OP ADDRESS MDR B A Decoder ALU OV Eurpides Montagne

University of Central Florida 71 05 Interrupt Cycle Including the stack mechanism If OV=1 Then PC NEWPC; MODE 1 (ABEND) If MP=1 Then PC NEWPC; MODE 1 (ABEND) If PI=1 Then PC NEWPC; MODE 1 (ABEND) IF I/O = 1 THEN MEM[SP] PC; SP SP +1 PC NEWPC; MODE1 ; If SVC=1, THEN MEM[SP] PC; SP SP +1 PC NEWPC; MODE 1; DECODER 00 Eurpides Montagne University of Central Florida 72

Program State Word including the SVC flag Interrupt Flags PC MASK Mode OV MP Eurpides Montagne PI I/O SVC

To be defined later University of Central Florida 73 Timer Interrupt What if a program has an infinite loop? We can add a time register, set to a specific value before a program stops, which is decremented with each clock tick When the timer reaches zero, the Timer Interrupt bit (TI) is set to 1, indicating that a timer interrupt has occurred and transferring control to the interrupt handler Prevents a program from monopolizing the CPU Eurpides Montagne University of Central Florida 74

Timer Interrupt cont. PC TI OV NewPC Timer MP PI Fence SVC Mode Supervisor Mode

SP Accumulator Eurpides Montagne User Mode University of Central Florida 75 Program State Word Interrupt Flags PC MASK Mode OV

MP Eurpides Montagne PI TI I/O SVC To be defined later University of Central Florida 76 Interrupt Vector Switching between user and supervisor modes must be done as quickly as possible

In the case of the VN machine, control is transferred to the interrupt handler, which then analyzes the flags and determines which is the appropriate course of action to take. A faster form of switching directly to the procedure or routine that handles the interrupt can be implemented using an interrupt vector Eurpides Montagne University of Central Florida 77 Interrupt Vector, cont. The idea of an interrupt vector consists of partitioning the interrupt handler into several programs, one for each type of interrupt. The starting addresses of each program are kept in an array, called the interrupt vector, which is stored in main memory. Eurpides Montagne

University of Central Florida 78 Interrupt Vector Structure For each type of interrupt, there is a corresponding entry in the array, called IHV. Instead of transferring control just to the Interrupt Handler, we specify the element in the array that corresponds to the interrupt that occurred. This way, the routine that handles that interrupt is automatically executed. Eurpides Montagne University of Central Florida 79 05 Interrupt Cycle with the Interrupt Vector

If OV=1 Then PC IHV[0]; Mode 1 If MP=1 Then PC IHV[1]; Mode 1 If PI=1 Then PC IHV[2]; Mode 1 0 1 OV 2 PI MP If TI=1 Then MEM[SP] PC; SP SP +1; 3 PC IHV[3]; MODE 1; 4 I/O

5 SVC Eurpides Montagne University of Central Florida TI 80 05 Interrupt Cycle with the Interrupt Vector, Cont. If I/O=1 Then MEM[SP] PC; SP SP +1; PC IHV[4]; MODE 1;

If SVC=1 Then MEM[SP] PC; SP SP +1; PC IHV[5]; MODE 1; DECODER 00; Eurpides Montagne University of Central Florida 0 1 OV 2 PI 3 TI

4 I/O 5 SVC MP 81 Program State Word (condition codes - CC) Interrupt Flags PC MASK Mode

OV MP PI TI I/O SVC To be defined later An additional field we can include in the PSW is called condition codes. Eurpides Montagne University of Central Florida

82 If the output of the ALU equals zero the zero flag (Z) is set to 1 PC NewPC 1 MP 1 MAR Address < Fence MEMORY

RTL-Address 3 SP stack 2 Fence (4000) OP ADDRESS MDR B A 0 Decoder ALU

OV Eurpides Montagne University of Central Florida A=0 Z 83 Program State Word (condition codes - CC) Interrupt Flags PC MASK CC Mode

OV MP PI TI I/O SVC To be defined later G Z L In addition to the Z flag we can incorporate two more flags: 1) G meaning greater than zero 2) L meaning less than zero Eurpides Montagne

University of Central Florida 84 Multiprogramming and Timers Multiprogramming: allowing two or more user programs to reside in memory If we want to run both programs, each program, P1 and P2, can be given alternating time on the CPU, letting neither one dominate CPU usage. Eurpides Montagne University of Central Florida 85 Process Concept In order to implement multiprogramming we need to utilize the concept of a process.

Process: defined as a program in execution Well explore this concept further in the next lecture. Eurpides Montagne University of Central Florida 86

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