EEE4084F Digital Systems - University of Cape Town

EEE4084F Digital Systems - University of Cape Town

EEE4084F Digital Systems Lecture 17 Programmable Logics & FPGAs FPGA Interns Lecturer: Simon Winberg Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) Outline for today Programmable Logic Devices What is so special about FPGAs FPGA interns Xilinx Slices Programmable Logic Devices EEE4084F

PLA PLD + SoC CPLD Programmable Chips In comparison to hard-wired chips, a programmable chip can be reconfigured according to application or user needs Provides a means to use the same chip(s) for a variety of different applications. Makes programmable chips attractive for use in many products, e.g. prototyping products. Further benefits are: Low starting cost (e.g. Web pack+ FPGA dev kit)

Risk reduction Quick turnaround time The term PLD refers to Programmable Logic Device which could technically be any of the programmable devices (i.e. PLA / CPLD / FPGA), in early work it often referred to a PLA but this is no longer a correct assumption. ASICs vs. Programmable Chips Application Specific Integrated Circuit (or ASICs) have a longer design cycle and higher engineering cost than using programmable chips. Still a need for ASIC: faster performance and lower cost for high volume Generally, programmable chips are suited to low to medium product production. (e.g. product runs needing under 10,000 chips)

PLAs, CPLDs and FPGAs Programmable logic chips variety in terms simplecomplex cheapexpensive PLA = Programmable Logic Array Simple: just AND and OR gates; but Cheap CPLA = Complex PLA Midrange: compose interconnected PLAs FPGA orders of

magnitude larger than CPLD FPGA = Field Programmable Gate Array Complex: programmable logic blocks and programmable interconnects; but Expensive Some examples of PLDs PLA: TIBPAL22V10-7C from Texas Instruments is a commonly used CPLD: The Altera MAXII and arguably the Altera FLEX as well

FPGA: Xilinx Spartan and Virtex range; Altera Cyclone and The Xilinx, Altera FPGA are probably the most commonly known manufacturers, others include: Lattice, Microsemi / Actel, Achronix So what? What is so special about FPGAs? ? So what? What is so special about FPGAs? FPGA A A sea

sea of of possibilities possibilities 01001010101000100101001010010100 10010010010100100101101001 100100110101011010011101 FPGAs A sea of possibilities The huge number of logic elements (LEs) within these chips, and their many PIO pins, makes it possible to implement large & complex digital systems in them. The ease and speed of programming them provides the ability to rapidly change the hardware (within ms timing) to adapt to application needs. Greater potential for testing and tweaking

designs before fabricating them as ICs Any Drawbacks? Only does the digital part still need analogue components, user interface, and circuitry that interacts with the outside world. Typically a slower clock than most fast CPUs nowadays (e.g. 100MHz clock speed). has lots of Typically pins that need to be soldered on, needing small track width and multilayer PCBs

A specialized form of development, combines the challenges of both s/ w and h/w s e r e H a few s t ack s u j wb dra Has a limited number of IO pins that can connect up with external

signals. Susceptible to EM disturbances, PCB and other components needs to be suitably placed to avoid interfering with functioning of FPGA. Often cant Eeek! achieve full utilization of PLBs Limitations of internal interconnects Place & route can take a long time to complete Things can get rather muddy! Structure of FPGA A

completely different architecture for PLAs was introduced in the mid-1980s that uses RAM-based lookup tables instead of AND-OR gates to implement combinational logic These devices are called field programmable gate arrays (FPGAs). The device consists of an array of configurable logic blocks (CLBs) surrounded by an array of I/O blocks FPGAs really dont have AND and OR gates, (they have a few) but rather just RAM lookup tables. EEE4084F FPGA Interns Skip to slide 22; already covered in text book but scan through these

slides to ensure you are well versed in these issues. FPGA internal structure Programmable interconnect Programmable logic blocks Image adapted from Maxfield (2004) Programmable logic element (PLE) (or FPLE*) Note: one programmable logic block (PLB) may contain a complex arrangement of programmable logic elements (PLE). The size of a FPGA or programmable logic device (PLD) is measured in the number of LEs (i.e., Logic Elements) that it has.

* FPLE = Field Programmable Logic Element Logic Elements Remember your logic primitives You already know all your logic primitives The primitive logic gates AND, OR, NOR, NOT, NOR, NAND, XOR AND3, OR4, etc (for multiple inputs). Pins / sources / terminators OR Ground, VCC Input Pin Input, output Storage elements Output Pin

JK Flip Flops Altera Quartus II representations Latches Others items: delay, mux Look Up Tables (LUTs) The usual strategy for implementing PLBs A simple but powerful approach to FPGA design is to use lookup tables for the PLBs. These are usually implemented as a combination of a multiplexer and memory (even just using NOR gates) Essentially, this approach is building complex circuits using truth tables (where each LUT enumerates a truth table)

examples follows Simple 3-LUT implementation for a PLB input values 000 001 0 010 1 011 0 100

1 101 0 110 111 0 1 1-bit output Any guesses as to what logic circuit this LUT implements? 1

8-bit static memory 3 3-bit input bus Simple 3-LUT implementation for a PLB Its an XOR of the 3 input lines!!! input lines output in 000 001 out 0

1 010 1 011 0 100 1 101 0 110 111

0 1 Mainstream* Programmable Logic Block (PLB) config_sync k inputs Configure synchronous or asynchronous response (i.e. a line from another big LUT). 0 k-input

LUT output DFF 1 clock Another example for implementing an alternate logic function. Image adapted from Maxfield (2004) * Used by manufacturers like Xilinx Logic block clusters (LBCs) and Configurable logic blocks (CLBs) Assume a k-input LUT for each logic block (LB) Assume N x LBs per logic cluster

BLEs in each logic clusters are fully connected or mostly connected The diagram shows the same input lines (I) are sent to each LB, in addition to each of the N LBs output lines. Each LB operates on 4 input lines at a time, and a MUX is used to decide which input to sample. The MUXs may be configured from a separate LUT, or could be controlled by the LB it is connected to. LB

N x LBs LB Diagram adapted from Sherief Reda (2007), EN2911X Lecture 2 Fall07, Brown University Xilinx L and M Slices Approach for configurable logic blocks (CLBs) Every slice contains four logic-function generators (or LUTs), eight storage elements, widefunction multiplexers, and carry logic. These elements are used by all slices to provide logic, arithmetic, and ROM functions. In addition to this, some slices support two additional functions: storing data using distributed RAM and shifting data with 32-bit registers. Slices that support these additional functions are called SLICEM; others are called SLICEL. SLICEM represents a superset of elements and connections found in all slices. Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs. In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL and a SLICEM. Source: pg 8 EEE4084F

Xilinx Slices SLICEM slices support additional functions; they are a superset of SLICELs; i.e. the have all the standard LEs plus some additions. Source: pg 9 SLICEL slices contain the standard set of LEs for the particular FPGA concerned. As the diagram shows, it looks a little less complicated than the design of a SLICEM. Source: pg 10

Disclaimers and copyright/licensing details I have tried to follow the correct practices concerning copyright and licensing of material, particularly image sources that have been used in this presentation. I have put much effort into trying to make this material open access so that it can be of benefit to others in their teaching and learning practice. Any mistakes or omissions with regards to these issues I will correct when notified. To the best of my understanding the material in these slides can be shared according to the Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) license, and that is why I selected that license to apply to this presentation (its not because I particulate want my slides referenced but more to acknowledge the sources and generosity of others who have provided free material such as the images I have used). Image sources: PLD illustration on title slide - Wikipedia Open Commons FPGA chip illustrations - Wikipedia Open Commons Stuck in Mud fickr (CC2 for free reuse and modification) Typing ninja Pixabay (public domain)

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