CS294-6 Reconfigurable Computing - Penn Engineering

CS294-6 Reconfigurable Computing - Penn Engineering

CS294-6 Reconfigurable Computing Day 5 September 8, 1998 Comparing Computing Devices Quotes

An engineer is a man who can do for a dime what any fool can do for a dollar. If it cant be expressed in figures, it is not science; it is opinion. -- Lazarus Long Motivation

Need to understand How costly (big) is a solution How compare to alternatives Cost and benefit of flexbility What we really want: Complete implementation of our application

For each architectural alternatives In same implementation technology w/ multiple area-time points Reality Seldom get it packaged that nicely much work to do so

technology keeps moving Deal with estimation from components technology differences few area-time points

Today Empirical Start sorting out custom vs. configurable spatial configurable vs. temporal FPGA Table

How many gates? gates in 2-LUT Now how many? Gates/unit area?

Usable gates? Gates Required? Depth=3, Depth=2048?

Gate metric for FPGAs? Day3: several components for computations compute element interconnect: space time

instructions Not all applications need in same balance Assigning a single capacity number to device is an oversimplification Exercise Admin

Simulation slow -> see fastsim alternative Exercise 1 more effort than anticipated Drop exercise 4 and rearrange due date SPACE1 --- ASAP SPACE2 --- original 9/10, try before 9/15 CYCLE --- 9/24

Density vs. Binding Time Full Custom Final Mask(s) Pre-mask

Density Gate Array FPGA startup

Binding Time Processor cycle MPGA vs. Custom?

AMI CICC83 MPGA 1.0 Std-Cell 0.7 Custom 0.5 Toshiba DSP Custom 0.3

Mosaid RAM Custom 0.2 GE CICC86 MPGA 1.0 Std-Cell 0.4--0.7

FF/counter 0.7 FullAdder 0.4 RAM 0.2 Metal Programmable Gate Arrays

MPGAs Modern -- Sea of Gates yield 35--70% maybe 5k/gate ? (quite a bit of variance) MPGA vs. FPGA MPGA (SOG GA)

5K2/gate 35-70% usable (50%) 7-17K2/gate net Xilinx XC4K 1.25M2 /CLB 17--48 gates (26?)

26-73K2/gate net Ratio: 2--10 (5) Adding ~2x Custom/MPGA, Custom/FPGA ~10x MPGA vs. FPGA

MPGA (SOG GA) gd~1ns Ratio: 1--7 (2.5) Xilinx XC4K

gates in 7ns 2-3 gates typical Processors and FPGAs Processors and FPGAs

Degrade from Peak: Processors Ops w/ no gate evaluations (interconnect) Ops use limited word width Stalls waiting for retimed data Degrade from Peak: FPGAs

Long path length --> not run at cycle Limited throughput requirement bottlenecks elsewhere limit throughput req. Insufficient interconnect Insufficient retiming resources (bandwidth)

Degrade from Peak: Custom/MPGA Solve more general problem than required (more gates than really need) Long path length Limited throughput requirement

Not needed or applicable to a problem Raw Density Summary Area MPGA 2-3x Custom FPGA 5x MPGA

Area-Time Gate Array 6-10x Custom FPGA 15-20x Gate Array Processor 10x FPGA Raw Density Caveats Processor/FPGA may solve more

specialized problem Problems have different resource balance requirements can lead to low yield of raw density Broadenning Picture Compare larger computations

For comparison throughput density metric: results/area-time normalize out area-time point selection high throughput density -> most in fixed area -> least area to satisfy fixed throughput target

Multiply FIR IIR/Biquad DES Keysearch

DNA Sequence Match Problem: cost of transform S1S2 Given: cost of insertion, deletion, substitution Relevance: similarity of DNA sequences

evolutionary similarity structure predict function Typically: new sequence compared to large databse DNA Sequence Match

Floating-Point Add (single prec.) Floating-Point Mpy (single prec.) Summary Raw densities (Area-Time)

FPGA/custom = 100x Processor/custom = 1000x Special-purpose functional units in processors/DSPs, much lower net benefit since need to control and interconnect Gap narrows (closes) as programmable can be

specialized

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