Configuration Memory Management for Adaptive Computing Systems

Configuration Memory Management for Adaptive Computing Systems

Exploration of Pipelined FPGA Interconnect Structures Scott Hauck Akshay Sharma, Carl Ebeling University of Washington Katherine Compton University of Wisconsin - Madison PipeRoute FPGA2003: Pipelining-aware Router for FPGAs Architecture-adaptive, based on Pathfinder Uses optimal 2-terminal, 1-delay router Greedy formulation for multi-delay, multi-terminal routing T1 S T2 2 RaPiD Coarse-grained, 1D, 16-bit, w/DSP Units Carl Ebeling @ UW-CSE Pipelined interconnect via Bus Connectors (BCs) ALU

GPR RAM GPR ALU GPR ALU GPR MULT RAM GPR RAM GPR 3 Pipelined Routing Results Area expansion due to pipelining Normalized to unpipelined circuit area 3

NORMALIZED AREA 2.5 2 1.5 1 0.5 Ave: 75% cost 0 0% 10% 20% 30% 40% 50% 60% 70%

% PIPELINED SIGNALS S T S T 4 Contributions Optimized PipeRoute Support multiple delays per BC (greedy preprocessor) Timing driven Pathfinders, worst-case criticality across signal RouteCost = Criticality * delay_cost + (1-criticality) * area_cost S T Arch. Exploration of RaPiD Pipelined Interconnects

Registered logic block (input/output/none) BC track length Delays per register/BC BC/non-BC routing mix Register-only logic blocks Goal: More efficient support of pipelined interconnects 5 Methodology Benchmarks Retimed, not C-slowed 80% Increase arch to fit (cells, tracks/cell) Variation around local minima 10 12

9 60% 10 8 7 40% AREA % PIPELINED SIGNALS Graphs 20% 8 6 5 6 DELAY

4 0% 4 3 2 2 1 NETLIST 0 0 1 2 3 4 5 6 7 Delays per BC/Reg AREA DELAY AREA*DELAY 6 Registers in Logic Blocks +

9 8 12 10 7 No Registers 6 Input Registers AREA + 5 6 4 3

+ 8 2 5% 20% 23% S T1 4 2 1 DELAY Output Registers 0 0 Out

None In Regs in Functional Units T2 AREA DELAY AREA*DELAY 7 Delays per Register/BC 1 Delay/BC 10 12 9 7 8

6 5 6 DELAY AREA 2 Delays/BC 10 8 4 3 2 4 15% 20% 30% 2 1 0 0 1 2 3 4 5 6 7 Delays per BC/Reg

AREA DELAY AREA*DELAY 8 BC Track Length Length 16 BC wires 9 25 8 20 7 Length 8 BC wires 15 DELAY AREA 6 5

4 10 3 2 1 17% 64% 69% 0 5 0 32 16 8 BC Track Length AREA DELAY 4 AREA*DELAY

9 Routing Resource Mix (BC vs. non-BC) 9 12 8 10 7 AREA 6 7/7 8 5 6 4 3 2 1 DELAY

5/7 4 19% 17% 18% 0 2 0 7/7 6/7 5/7 4/7 3/7 Proportion BC Tracks AREA DELAY AREA*DELAY 10 GPRs per Cell GPR roles: Registers from computation Passthrough for changing tracks 12 7

6 per cell 10 6 8 AREA 5 4 6 3 DELAY 8 4 2 9 per cell 1

6% 23% 22% 0 2 0 5 AREA 6 7 8 9 10 GPRs per Cell DELAY AREA*DELAY 11 Overall vs. RaPiD-I 1.4 RaPiD-I

0.6 0.4 sort_rb sort_g firsymeven 0 imagerapid Ave: 1% 18% 19% sobel 0.2 matmult4 1 BC / cell (16 LBs long) 5/7 BC tracks 3 registers / BC 9 GPRs / cell registered inputs 0.8 cascade

1 fft16 Post-Explore 1.2 firtm 1 BC / cell (13 LBs long) 5/7 BC tracks 3 registers / BC 6 GPRs / cell registered outputs Ratio Post/RaPiD-I Proportion non-BC Tracks AREA

DELAY AREA*DELAY 12 Overall Pipelining Cost 1.6 1.4 Normalized Area 1.2 1 0.8 0.6 0.4 Ave: 18% cost 0.2 0 0% 10% 20% 30%

40% 50% 60% 70% 80% % Pipelined Signals S T S T 13 Conclusions Router for arbitrary pipelined architectures Timing-driven Supports multiple delays at each register site Good quality: <18% of pseudo-lower bound (non-pipelined) area

Architecture Exploration of RaPiD Parameters: Registered inputs on functional units Length 16 wires 3 delays per BC/register 2/7 non-registered, 5/7 registered wires 9 GPRs/cell to improve flexibility Delay: spacing of registers CRITICAL, too close better than too far 19% area*delay improvement over RaPiD-I (primarily delay) 14 *** End of Talk Marker *** 15 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS S T 16 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS

S T 17 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS S T 18 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS S T

19 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS S T 20 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS S T 21 1-Delay Two Terminal Can do optimal routing for 1-delay routes via BFS

S T 22 N-Delay Two Terminal Greedy Approximation via 1-Delay Router S T 23 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route S

T 24 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement S T 25 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement

S T 26 N-Delay Two Terminal Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement S T 27 N-Delay Two Terminal

Greedy Approximation via 1-Delay Router Find 1-delay route While not enough delay on route Replace any 0-delay segment with cheapest 1-delay replacement S T 28

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