MET 3821/14/2008PLC Fundamentals –Ladder Logic FundamentalsMET 382Controls & Instrumentationfor AutomationSpring ‘08T.E. KostekTopics PLC programming languagesAnatomy of a ladder programLogic functionsLogical continuity vs. electrical continuityI/O MappingMastering examine on and examine offinstructionsThe PLC scanning process2Ladder Logic Fundamentals1

MET 3821/14/2008PLC Programming Languages In the United States, ladder logicg is the most ppopularpmethod used to program a PLC This course will focus primarily on ladder logic programming Other programming methods include:Function block diagrams (FBDs)Structured text (ST)Instruction List (IL)Sequential function charts (SFCs)3Anatomy of a Ladder ProgramInput Instructions (conditions)Output Instructions(actions)Rung 0Rung 1Rung 2Left power railLadder Logic FundamentalsRight power rail42

MET 3821/14/2008Anatomy of a Ladder Program(cont’d) Input instructions are entered on the left Output instructions are entered on the right The power rails simulate the power supply linesL1 and L2 for AC circuits and 24 v and ground forDC circuitsi it Most PLCs allow more than one output per rung5Anatomy of a Ladder Program(cont’d) The processor (or “controller”)controller ) scansladder rungs from top-to-bottom and fromleft-to-right.The basic sequence is altered whenever jumpor subroutine instructions are executed.6Ladder Logic Fundamentals3

MET 3821/14/2008Anatomy of a Ladder Program (cont’d)A33-rungrung example ladder program7Anatomy of a Ladder Program (cont’d)Rung CommentRung NumberDescription assigned to alias tagAlias tag pointing to base addressBase addressInput Instruction8Ladder Logic Fundamentals4

MET 3821/14/2008Logic Functions PLC programming is a logical procedure In a PLC program, “things” (inputs and rungs)are either TRUE or FALSE If the proper input conditions are TRUE:The rung becomes TRUE and an output action occurs(for example, a motor turns on) If the proper input conditions are not TRUE:The rung becomes FALSE and an output action doesnot occur9Logic Functions (cont’d) Ladder logicg is based on the followingglogic functions:ANDOR Sometimes called “inclusive OR”Exclusive OR10Ladder Logic Fundamentals5

MET 3821/14/2008Logic Functions - ANDInput 1ANDO t tOutputLogicInput 2Input 10011Input 20101Output0001ContactsANDedtogether0 Æ False1 Æ True()11Logic Functions - ORInput 1OROInput 2Input 10011ContactsORedtogetherLadder Logic FundamentalsO t tOutputLogicInput 20101Output01110 Æ False1 Æ True()126

MET 3821/14/2008Logic Functions - Exclusive ORIn addition to ANDing and ORing, the Exclusive OR (XOR) isalso useful. When the inputs are DIFFERENT, the XORt t isi true.toutputInput 1XOROutputLogicInput 2Input 10011Input 20101Output01100 Æ False1 Æ True13Logic Functions (cont’d) Example 1 – Inputs ANDed together in seriesInputsOutputThree input instructions ANDed together.All 3 input instructions must betrue in order to energize the output14Ladder Logic Fundamentals7

MET 3821/14/2008Logic Functions (cont’d) Example 2 – Inputs ORed together in parallelInputsOutputThree input instructions ORed together.If any of the 3 input instructions aretrue the output will be energized15Logic Functions (cont’d) Example 3 – A combination of ANDing and ORing16Ladder Logic Fundamentals8

MET 3821/14/2008Logical Continuity Logical continuity in a ladder rung occurs whenthere is a continuous path of TRUE conditionsfrom the left power rail to the output instruction(s) When there is logical continuity, the rungbecomes true and the output becomes energized17Logical Continuity – Example 1Rung FalseRung 0TFTThis input instruction is falseThis input instruction is trueRung FalseRung 1FRung 2FRRungTTrueTTTLeft power railLadder Logic FundamentalsRight power rail189

MET 3821/14/2008Logical Continuity – Example 2Virtual power flow (not actual current flow)Path of logical continuityRung truedue to thisbranchTRUE conditions are highlighted in greenon the programming panels displayÆ PLCPLC--5 Systems19Logical Continuity vs.Electrical Continuity Electrical continuity in an input circuit, occurs when thereis a complete path for current to flow. A PLC input circuit is a simple series circuit consisting of a:Power supply,Switch, and aLoad When there is electrical continuity, a bit in the PLCsmemory (sometimes called the input image table) is set toa 1.20Ladder Logic Fundamentals10

MET 3821/14/2008Electrical Continuity 24vNormally open (N.O.) pushbutton [shown pushed]COMInput ModuleInputCircuitry21Electrical Continuity Power supply is implied- 24vCOMInput ModuleInputCircuitryScrew terminalsPower railPower rail22Ladder Logic Fundamentals11

MET 3821/14/2008Logical vs. Electrical Continuity Note: It’s possible to have electrical continuity and nothave logical continuity (and vise versa).Control Wiring Diagram:Ladder Program:PB0 - N.O. pushbutton(shown pushed)This instruction is false whenthe pushbutton is pushedI PB0I PB0()No Logical ContinuityElectrical Continuity23I/O Mapping Every discrete input is assigned to a specific bitin the PLC’s memory (input image table)If there is electrical continuity, the bit is set to a 1If there is no electrical continuity, the bit is reset to a 0 Every discrete output is assigned to a specific bitin the PLC’sPLC s memory (output image table)In order for an output to turn on, its associated bitmust first be set to a 124Ladder Logic Fundamentals12

MET 3821/14/2008PLC Data Table1 word (16 bits)Inputmoduleinput, PB1Input Image Table(only 1 word shown)10021614 1206 04000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 005 03151107011713Note: Bit addressesare given in octal foran Allen-BradleyPLC-5 systemThe bits arenumbered 0 – 17I:XXX/10output , LT1Output Image Table(only 1 word shown)RO:XXX/01Output Module10021614 1206 04000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 005 03151107011713Æ PLCPLC--5 Systems25I/O MappingOutput Image Table inRSLogix 5 softwareInput Image Tablein RSLogix 5 softwareÆ PLCPLC--5 SystemsLadder Logic Fundamentals2613

MET 3821/14/2008I/O MappingOutput Image Table in RSLogix 5:O:005 is a 16 bitword address:O:005/07 is theaddress of a bitwhich resides inthe word O:005Æ PLCPLC--5 Systems27I/O MappingInput Image Table in RSLogix 5:Æ PLCPLC--5 SystemsLadder Logic Fundamentals1 word 16 bits (bits arenumbered in octal for a PLC-5)2814

MET 3821/14/2008I/O MappingControlLogix tag database:Alias tag(a pointer to a base address)Current tagvalueBase address(real address)Æ ControlLogix Systems29Mastering Examine On &Examine Off Instructions Discrete input devices have normallyopen (N.O.) and/or normally closed (N.C.)contacts.Example: Pushbuttons can be purchased witheither N.O. or N.C. mechanical contacts.“Normally” implies the state of the contactswhen you are NOT pushing the button.30Ladder Logic Fundamentals15

MET 3821/14/2008Mastering Examine On &Examine Off Instructions Normally open (N.O.) vs. normally closed (N.C.)contacts:ContactResistance betweenType: contacts when NOT pushed:N.O.N.C.Resistance betweencontacts when pushed:Infinite ohmsZero ohmsZero ohmsInfinite ohms31Mastering Examine On & Examine OffInstructions PLC programs have both normally open andnormally closed input instructions.Normallyy closed inputp instructionNormally open input instruction32Ladder Logic Fundamentals16

MET 3821/14/2008Mastering Examine On & Examine OffInstructions The Examine On InstructionThis input instruction examines the specifiedbit for a logic 1. If the bit is a 1, the instructionis true, otherwise the instruction is false.This is generally known as anormally open input instruction.33Mastering Examine On & Examine OffInstructions The Examine On InstructionThis is the address assignedto the instruction (I:007/00).Note: This instruction must beassigned a bit addressaddress, not aword address.This is the instructionÆ PLCPLC--5 Systems34Ladder Logic Fundamentals17

MET 3821/14/2008Mastering Examine On & ExamineOff Instructions The Examine Off InstructionThis input instruction examines the specifiedbit for a logic 0. If the bit is a 0, the instruction istrue, otherwise the instruction is false.This is generally known as anormally closed input instruction.35Mastering Examine On & ExamineOff Instructions Examine On instructions are also called:XIC, eXamine If Closed Examine Off instructions are also called:XIO, eXamine If OpenNote: The terms Examine on, Examine off, Examine ifclosed (XIC), and Examine if open (XIO) are unique toAllen-Bradley PLCs.36Ladder Logic Fundamentals18

MET 3821/14/2008Mastering Examine On & ExamineOff Instructions Examine On and Examine Off Instructionsthat are True are highlighted green in thePLC programming software:TrueFalse37Mastering Examine On & ExamineOff Instructions Approgramgcan Examine On ((or Examine Off)) realinputs, real outputs, internal storage bits, timerdone bits, etc.Examine ONa real inputExamine OFF aninternal storage bitExamine ONa real output38Ladder Logic Fundamentals19

MET 3821/14/2008Mastering Examine On & Examine Off Instructions Input and output field devices are wired to PLC discreteInput/Output (I/O) modules. How the system functionsdepends on the program! 24 VDCStart(N.O.)StopOutpuutsPLCInputssTwo pushbuttonswired to two PLCinputs120 VAC(N.C.)FANA fan is wired toa PLC output(Continued on next slide )39Mastering Examine On & Examine Off InstructionsHow the system functions depends on the program:The inputs could be programmed as two inputs ANDed together:Or, the inputs could be programmed as two inputs ORed together:In either case, the wiring is the same!The PLC program logically connects the inputdevices to the output actuators through the PLCprogram!Ladder Logic Fundamentals4020

MET 3821/14/2008Mastering Examine On & Examine Off InstructionsInput field deviceswired to the PLCThe PLC Data TableInstructions in thePLC programElectrical ContinuityInput Image Table BitLogical Continuity 24vStart(N.O.)Current flows if button ispressed0 or 1The bit representing the pushbutton is:True if the bit is a 1ON (set to a 1) if there iselectrical continuity 24vStart(N.C.)OFF (reset to a 0) if there isNO electrical continuityTrue if the bit is a 0Current flows if button isNOT pressed41Mastering Examine On & Examine Off InstructionsOutput field deviceswired to the PLCThe PLC Data TableInstructions in thePLC programElectrical ContinuityOutput Image Table BitLogical Continuity120 VAC0 or 1FANOutput turns on when thebit ini theth outputt t imageitable is a 1 (voltage isapplied across the outputterminals and current flowsin the output circuit)The bit representing the fanoutput is:ON (set to a 1) if there islogical continuityOFF (reset to a 0) if there isNO logical continuityThe output image tablebit is set to a 1 when therung is true or is reset toa 0 when the rung isfalse42Ladder Logic Fundamentals21

MET 3821/14/2008The Scanning Process Scan refers to the continuous andsequential process of:Reading the PLC inputsExecuting the ladder program (rung-by-rung)Updating the PLC outputs43The Scanning Process The scan sequence can be broken intotwo functional parts:The Program Scan Scan the ladder programThe I/O Update Scan Write outputs, Read inputs44Ladder Logic Fundamentals22

MET 3821/14/2008The Scanning Process The Program Scan:For each rung executed,executed the PLC processor will: Examine the status of the input image table bits, Solve the ladder logic in order to determine logicalcontinuity (is the rung true?), Update the appropriate output image table bits, ifnecessary.Note: The output will not actually be energized untilthe I/O update part of the scan.45The Scanning Process The I/O Update Scan:Copy the output image table status to the ALL ofthe output terminals (discrete output circuits) Power is applied to the output device if it’s outputimage table bit has been previously set to a 1.Copy the status of ALL of the input terminals tothe input image table If an input is active (i.e., there is electrical continuity),the corresponding bit in the input image table will beset to a 1.46Ladder Logic Fundamentals23

MET 3821/14/2008The Scanning ProcessRead inputsAll inputTerminalsInput ImageTable(Solve the ladder program)(update output image table asnecessary)[END]Update outputsAll outputTerminalsOutput ImageTable47The Scanning Process In a ladder program, a specific output address (e.g.,O:013/02) should NOT be referenced on more than oner ng!rung!This is sometimes called “duplicate coils”Using duplicate coils will cause unpredictable operation and shouldbe avoidedWhen using duplicate coils “the last rung wins”See example on next slideContinued on next slide Ladder Logic Fundamentals4824

MET 3821/14/2008Duplicate Coil ExampleProblem: Rungs 11 and 19 both reference the same output address:Solution: Edit the ladder pprogramgas follows:Problem corrected, this output is only used once in the entire program49The Scanning Process The actual scan time is a function of:Th speedThed off theth processor moduled lThe length of the ladder programThe type of instructions executedThe actualTht l ladderl dd true/falset /f l conditionsditi((e.g.,jump instructions, subroutines, etc.)50Ladder Logic Fundamentals25

MET 3821/14/2008The Scanning Process The actual scan time is calculated and stored in the PLCsmemoryThe PLC computes the scan time each time the END instruction isexecutedScan time data can be monitored via the PLC programmingsoftware (e.g., RSLogix 5)Scan time data is addressable and can therefore be referenced inthe PLC program TypicalTi l scan titime ddatat iincludes:l dThe maximum scan timeThe last scan time51The Scanning Process Allen-Bradley PLCs generally have 3modes of operation:Run Mode When placed in the RUN mode, the processor beginsthe scanning process as previously describedProgram Mode When placed in the PROGRAM mode, the processorstops scanning the ladder program and (typically) allthe outputs are turned offTest Mode Ladder Logic FundamentalsThe TEST mode is identical to the RUN m